Chip identification is required in order to provide proper identification of chips that are, for example, manufactured using different manufacturing runs. Chip identification may also be important in order to easily identify chips that may be required for certain applications. For example, backside identification of chip packages is required in order to maintain order in routine production, and to recover from minor disruptions related to loss of normal order. For server products or other products using Temporary Chip Attach (TCA) and/or burn-in processing, chip labels are critical in assigning and maintaining separate populations of “good” and “bad” parts, and different speed sorts that may be required for different final modules. For example, for a population where normal order has been lost, without backside chip identification, TCA remount would be required to remove “bad” chips which, in turn, would negatively impact shipments and revenue.
By using backside identification, it is possible to identify and remove populations of parts from stock based on wafer/lot origin, in response to the identification of a maverick or “non-conforming” population. Also, as particular chips may be required for physical failure analysis (PFA), it may be necessary to identify such chips for analysis. In addition, identification of the chips is important in order to perform a resort when parts become mixed in stock or to identify “bad” chips during the resort. All of this can only be readily accomplished if wafer and chip identification are physically encoded into the package for an operator to read at an inspection station.
Historically, for ceramic substrate parts, a laser backside chip scribe is employed to provide this information. This has worked well as the coefficient of thermal expansion (CTE) of the Silicon chip and the ceramic substrate are relatively close. For example, the CTE of a ceramic substrate is about 8-10 ppm/° C. and the CTE of the chip is about 3 ppm/° C. A larger CTE difference between chip and substrate, as is the case with chips assembled on organic substrates, will result in increased risk of chip breaking during assembly. On the other side, laser marking decreases the breaking strength of a chip. FIG. 1 shows the effect of laser marking on the breaking strength of Silicon chips.
With flip chip ball grid array (FCPBGA) organic laminate parts, a backside chip scribe has been shown to mechanically weaken the chip, such that it is more likely to fail under the influence of normal warpage stresses during thermal excursion. That is, the physical scribe on the backside of the chip provides a weakened area that can be a “break point” during warpage of the chip, which results from thermal expansions and contractions during normal manufacturing processes.
By more specific example, in organic chip technology, an organic substrate is attached to the chip by use of an epoxy underfill. The package is then subjected to a high temperature, e.g., about 150° C. for underfill cure. During cool down of the package, the organic substrate (i.e., laminate) shrinks more than the chip. This results in the backside of the chip being placed in tension. This is due to the differences in CTE between the chip and the organic laminate (e.g., CTE of the chip is about 3, whereas the CTE of the organic laminate is about 20). As a result of this tension, the chip has a tendency to fail at the scribe. As such, the chip backside scribe for organic laminates has been found to be unacceptable.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.